With an information processing unit such as a processor, and so forth, if data transfer is efficiently performed, this will lead to enhancement in performance of the information processing unit on the whole. In the case where the information processing unit performs transfer of a massive amount of data, if such transfer is carried out with a CPU (a general purpose processor), this will cause delay in processing that is to be primarily performed by the CPU, so that the performance of the unit on the whole undergoes deterioration.
Accordingly, with a current information processing unit, data transfer is performed by use of a data transfer processing unit, generally called a direct memory access controller (DMAC), substituting for the CPU. Hence, it becomes possible for the CPU itself to perform other processing while the DMAC performs the data transfer only by setting a data transfer activation command to the DMAC.
With such a method as described, the CPU needs to set the data transfer activation command one by one to the DMAC every time data transfer is required. Further, there arises the need for monitoring whether or not the DMAC is in operation.
If the CPU performs setting of the data transfer activation command every time data transfer is performed as described, this will not be seen as large overhead in the case of a transfer data length being long, however, in the case of the transfer data length being short, this will be seen as large overtime, thereby interfering with enhancement in performance.
As a method for reducing the number of times the data transfer activation command is set by the CPU, there has been proposed a method called a command chain, or CCW (channel command word) chain. With the command chain, instead of the data transfer activation command being given to the DMAC via the CPU every time data transfer is performed, a list of all data transfer commands is preset in a memory, and upon the CPU giving an instruction to perform data transfer by starting from the data transfer command at the top of the list, the DMAC sequentially reads the data transfer commands in the memory, thereby performing data transfers.
With this method, since the CPU performs only a first activation of a data transfer, and the DMAC itself performs activation(s) of the data transfer command(s) with respect to data transfers thereafter, the number of times the data transfer activation command is set by the CPU will be only one. Hence, it becomes possible for the CPU to allocate time required for setting the data transfer command before to other processing.
Now, there have been known a technology (for example, JP-A No. Heill(1999)-212898) for enabling continuous processing without interruption in writing to a hard disc in the case of data transfer using the CCW (channel command word) chain intended for a data chain, and a technology (for example, JP-A No. 2006-277583) whereby a return code for transfer on a CCW unit is checked, and CCW to be next executed is decided according to the return code, thereby alleviating a processing burden on a host.